International Wafer-Level Packaging Conference

Country: USA

City: San Jose

Abstr. due: 10.04.2018

Dates: 23.10.18 — 25.10.18

Organizing comittee e-mail: jenny@smta.org

Organizers: SMTA; Chip Scale Review

 

The SMTA and Chip Scale Review are pleased to announce plans for the 15th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. This premier industry event explores leading-edge design, material, and process technologies being applied to Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.

The IWLPC Technical Committee would like to invite you to submit an abstract for this program.

The conference includes three tracks with two days of technical paper presentations covering: Wafer-Level, 3D, TSV, and Integrated System Packaging. Also we will offer professional development courses.

Wafer-Level Packaging:
Wafer Level Chip Scale Packaging (WLCSP), Flip-chip, Fan-Out and Redistribution, Wafer and Device Cleaning, Nanotechnology, Quality, Reliability, and COO.

3D Package Integration:
3D WLP, Thru Silicon Vias (TSV), Thru Glass Vias (TGV), Silicon Interposers, Stacking Processes (W2W, D2W, D2D), IC Packaging Substrates, TSV Integration methods (FEOL vs BEOL.)

Advanced Integrated Systems and Devices:
System packaging leveraging wafer-level process technologies including: System-in-Package (SiP), MEMS, sensors, Package-on-Package (PoP), embedded die and passives, and EMI shielding methods.

Advanced Wafer-level Manufacturing and Test
Advances in wafer-level manufacturing processes, equipment and materials including: novel process or material technologies, improved equipment throughput and productivity, control methodologies (SPC, APC, FDC), factory output & cycle time improvements, advanced automation technologies, warped wafer handling, wafer level test methods, wafer level vs. singulated unit test for WLP, and TSV test methods.

Conference Web-Site: http://www.iwlpc.com/call_for_papers.cfm