17th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition
City: San Jose
Abstr. due: 03.04.2020
Dates: 13.10.20 — 15.10.20
Organizing comittee e-mail: firstname.lastname@example.org
Organizers: SMTA and Chip Scale Review
The SMTA and Chip Scale Review are pleased to announce plans for the 17th Annual International Wafer-Level Packaging Conference and Tabletop Exhibition. This premier industry event explores leading-edge design, material, and process technologies being applied to Wafer-Level Packaging applications. There will be special emphasis on the numerous device and end product applications (RF/wireless, sensors, mixed technology, optoelectronics) that demand wafer level packaging solutions for integration, cost, and performance requirements.
The conference includes three tracks with two days of technical paper presentations covering: Wafer-Level, 2.5D & 3D packaging, and Advanced Manufacturing & Test. Also, the conference offers professional development courses (PDCs).
Wafer Level Chip Scale Packaging (WLCSP), Flip-chip, Fan-Out and Redistribution, Wafer and Device Cleaning, MEMS, sensors, Nanotechnology, Quality, Reliability, and COO.
3D Package Integration:
3D WLP, Thru Silicon Vias (TSV), Thru Glass Vias (TGV), Silicon Interposers, Stacking Processes (W2W, D2W, D2D), IC Packaging Substrates, TSV Integration methods (FEOL vs BEOL), Package-on-Package (PoP), embedded die and passives, and EMI shielding methods.
Advanced Wafer-level Manufacturing and Test
Advances in wafer-level manufacturing processes, equipment and materials including: novel process or material technologies, improved equipment throughput and productivity, control methodologies (SPC, APC, FDC), factory output & cycle time improvements, advanced automation technologies, warped wafer handling, wafer level test methods, wafer level vs. singulated unit test for WLP, and TSV test methods.
Conference Web-Site: https://www.iwlpc.com/call_for_papers.cfm