10th International Symposium on Networks-on-Chip (NOCS 2016)

Країна: Японія

Місто: Nara

Тези до: 05.02.2015

Дати: 31.08.16 — 02.09.16

Область наук: Технічні;

Е-мейл Оргкомітету: matutani@arc.ics.keio.ac.jp

Організатори: Keio University, Intel


The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

NoC Architecture and Design
Network architecture (topology, routing, arbitration)
NoC Quality of Service
Timing, synchronous/asynchronous communication
Network interface issues
NoC design methodologies and tools
Mapping of applications onto NoCs
Signaling and circuit design for NoC links
NoC at the Un-Core and System-level
Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols, and NoCs
NoC support for memory and cache access
OS support for NoCs
Programming models including shared memory, message passing, and novel models
Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks
Novel NoC Technologies
New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc
NoCs for 3D and 2.5D packages
Package-specific NoC design
Optical, RF, and emerging technologies for on-chip/in-package interconnects
NoC Application
NoC case studies
Application-specific NoC designs
NoC designs for heterogeneous many-core systems, fused CPU-GPU architectures, FPGA-based systems, etc
NoC Analysis, Verification, and Modeling
Modeling, simulation, and synthesis of NoCs
Verification, debug, and test of NoCs
Metrics and benchmarks for NoCs
Scalable modeling of NoCs
NoC Optimization
For power/energy efficiency
For thermal efficiency and darksilicon
For dependable architectures
For communication efficient algorithms
Submission Rules

Веб-сторінка конференції: http://www.arc.ics.keio.ac.jp/nocs16/index.html

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